Herebelow reference is made to several references that are listed near the close of this disclosure. Thus, numerals in brackets ([1], [2], etc.) are intended to refer to references in that list.
As processor speeds continue to increase at a much higher exponential rate than DRAM speeds, memory latencies will soon exceed 1000 cycles. With such non-uniform access times, the flat memory model that was made practical by deeply pipelined superscalar processors with multi-level cache memories will no longer be tenable due to the inexorable effects of Amdahl's Law. The most common approach to this problem is hardware multi-threading, but multi-threading requires either abundant independent applications, or well-parallelized monolithic applications, and neither is easy to come by.
In U.S. Pat. No. 6,308,261 (“Computer System Having an Instruction for Probing Memory Latency”), as well as European Patent Nos. EP 0933698A2 (“Probing Computer Memory Latency”) and EP 0933698A3 (“Probing Computer Memory Latency”), Dale C. Morris and Douglas B. Hunt have proposed to maintain availability status for registers in a computer system, wherein the availability status indicates whether an instruction attempting to read a particular register (which can be the destination of a memory load instruction) will stall. A memory probe instruction can be used to alter the program execution path based on the availability status of one or more of the registers. In one embodiment, a latency probe instruction retrieves the availability status of a register to another register so that a conditional branch instruction can determine the program execution path based on the availability status. In another embodiment, a conditional branch instruction can query the availability status of a register directly to determine the program execution path. Conceptually, the availability status is the same as the presence bit used in I-structures [1] or tagged memory.
A need has been recognized in connection with providing a more broadly applicable and more effective approach than in conventional arrangements such as those contemplated by Morris and Hunt and by others.